Data storage device with overlapped buffering scheme

ABSTRACT

A data storage device is disclosed that, in response to a data output request, outputs stored data beginning with a selected output start address. The disclosed data storage device is characterized in that the selectable output start addresses exhibit such slight spacings from one another that the amount of data storable between neighboring output start addresses is smaller than the amount of data output in response to a data output request. As a result thereof, the plurality of accesses onto the data storage device can be reduced to a minimum.

The present invention is directed to a device according to the preambleof patent claim 1, i.e. a data storage device that, in response to adata output request, outputs stored data from a selected output startaddress.

One of the most important properties that a data storage device mustexhibit is comprised therein that data stored therein can be read out asquickly as possible. This is particularly true when the data storagedevice in a matter of a program memory for a program-controlled unitsuch as, for example, a microprocessor, microcontroller or the like. Thedata storage devices, which are usually employed as program memories(ROMs, EPROMs, Flash EPROMs, DRAMs, etc.) are usually not in theposition to output the (command) data stored therein as fast as modernprogram-controlled units can process them. Fast, static RAMs aretherefore often employed as buffer memories (Caches). These Caches makeit possible that the program-controlled unit does not always have toretrieve the required data from the slow program memory but can oftenobtain them from the fast Cache.

As a result thereof, in particular, program sections having a linearexecution (exhibiting no skips) can be implemented very fast. This,however, does not apply—or only applies in limited fashion—to programsections having commands such as, for example, branch commands and thelike that interrupt the linear execution. In many instances, the commandto be executed after a branch is not available in the Cache, for whichreason the slow program memory must continue to be accessed in thesecases as previously.

Added thereto as a complicating factor is that the command that is to beretrieved from the program memory after a branch or the like is oftennot completely contained in the data that are output by the programmemory in response to a data output request. This can even be the casewhen the data set that is output in response to a data output request isrelatively large (substantially greater than the command length) with,for example, 4 or 8 bytes. In such cases, two read accesses onto theprogram memory are required in order to be able to obtain the datarepresenting the next command.

This is a not inconsiderable problem, particularly since approximatelyevery third command in typical programs is a branch instruction.

The present invention is therefore based on the object of finding ameasure with which the offering of data that represent successorcommands after branches or the like can be speeded up.

This object is inventively achieved by the features claimed in thecharacterizing part of patent claim 1.

It is provided in the accord therewith that the selectable output startaddresses exhibits such slight spacings from one another that the dataset that can be stored between neighboring output start addresses issmaller than the data set output in response to a data output request.

Due to the slight mutual spacings of the selectable output startaddresses, an output start address—leaving a few exceptions out ofconsideration—can always be applied with which the data representing acommand can be read out from the program memory (the data storagedevice) on the basis of a single access.

As a result thereof, the time that is required in order to offer datarepresenting successor commands after branches or the like can bereduced to a minimum in an astonishingly simple way.

The suitable selection of the output start address can thereby ensue,for example, upon employment of data referred to below as adaptationdata that are applied to the data storage device in addition to the datathat are otherwise standard and with which a determination is made as towhether and, potentially, to what extent the output start address to beemployed is greater or smaller than the address that is defined by theaddress data likewise applied to the data storage device as output startaddress. As a result thereof, the output start address can beindividually determined in dynamic fashion in an extremely simple wayand given unmodified retention of the standard addressing of the datastorage device.

Advantageous developments of the invention can be derived from thesubclaims, the following description and from the Figures.

The invention is explained in greater detail below on the basis ofexemplary embodiments with reference to the Figures. Shown are:

FIG. 1 the schematic structure of a first exemplary embodiment of thedescribed data storage device; and

FIG. 2 the schematic structure of second exemplary embodiment of thedescribed data storage device.

The data storage devices described in greater detail below aresemiconductor memories accommodated in an integrated circuit, RAMs,ROMs, EPROMs, flash-EPROMs or the like employed as program memories tobe more precise; however, the data storage devices can alsofundamentally be a matter of other, arbitrary data storage devices.

The data storage devices comprise a plurality of memory cells (designedfor respectively storing one data bit) that are interconnected in aknown way matrix-like to form a memory cell field comprising a pluralityof rows and columns. It thereby proves especially advantageous in viewof the access time when the individual memory cell field rows comprise agreat number of memory cells. In the example under consideration, thememory cell field rows respectively contain 256 memory cells; of course,arbitrarily more or fewer memory cells can also be provided per memorycell field row.

Upon readout of data stored in the data storage device, a data wordrespectively comprising a predetermined data set is output. In theexample under consideration, a data word covers 64 bits; of course, adata word can also comprise more or fewer bits.

The memory cells can be addressed via address data applied to the datastorage device an adaptation data likewise applied to the data storagedevice. The addressing determines the memory cell from which data arewritten into the memory cell when writing the data storage device or,respectively, beginning with which memory cell data stored in the datastorage device are output when reading the data storage device. Theaddress of the memory cell beginning with which data stored therein areoutput when reading the data storage device is referred to below asoutput start address.

The following comments are limited to the readout of data from the datastorage device. The readout of data from the data storage device isinitiated by a data output request. In response to a data outputrequest, 64 data bits (a 64-bit data word) are output from the outputstart address defined by the address data and the adaptation data.

The selectable output start addresses thereby exhibit such slightspacings from one another that the data set that can be stored betweenneighboring output start addresses is smaller then the data set outputin response to a data output request.

The data storage device is addressed in the standard way by the addressdata applied to the data storage device. i.e., the output startaddresses definable by the address data follow one another in steps thatremain of constant size, whereby the step width corresponds exactly tothe plurality of bits output in response to a data output request. Inthe case under consideration, wherein the data can be written and readin units of 64 bits, this means that the addresses of the bits numbers0, 64, 128 and 192 of each and every memory cell field row can bedefined as output start addresses via the address data.

The adaptation data applied to the data storage device defines whetherand, potentially, to what extent the output start address to be employedis greater or smaller then the output start address defined by theaddress data. i.e., a definition can be made as to whether the outputstart address defined by the address data or an address that is more orless greater or smaller is employed as output start address.

This can be accomplished, for example, in that the interface between thememory cell field and the output terminals of the data storage device iscorrespondingly modified. Said interface has hitherto composed of one ormore multiplexers, with which the bits

-   -   0 through x−1    -   x through 2x−1        -   . . . , or    -   (n−1) x through nx−1        of the respectively selected memory cell field row are        optionally through-connected onto the output terminals, whereby        x represents equal to the plurality of bits per output data word        and amounts to 64 in the example under consideration, and        whereby n represents the plurality of data words storable per        memory cell field row and amounts to 4 in the example under        consideration.

What is achieved by one or more additional multiplexers and/or amodification of the existing multiplexers and (additional) drive thereofby the adaptation data is that the bits

-   -   0 through x−1 or y through x−1+y    -   x through 2x−1 or x+y through 2x−1+y        -   . . . , or    -   (n−1) x through nx−1 cr (n−1) x+y through nx−1        of the respectively selected memory field row are optionally        through-connected onto the output terminals, whereby the new        parameter y references an offset relative to the output start        address defined by the address data.

The practical realization of an arrangement with which the bits 0through 63 or the bits 16 through 79 of a memory cell field row areoptionally through-connected onto the output terminals of the datastorage device (offset y=16) is illustrated in FIG. 1.

The selected memory cell field row is thereby referenced with referencecharacter SZFZ, the memory cells thereof are referenced with thereference characters SZ00, SZ01, SZO2, . . . , the multiplexer isreferenced with the reference character MUX and the control signal thatcontrols the latter is referenced with the reference character C,whereby the control signal C driving the multiplexer MUX corresponds tothe adaptation data or is based thereon.

When the control signal C of the multiplexer MUX has the value 0, then,as was hitherto standard, the data stored in the memory cells SZ00through SZ63 are through-connected onto the output terminals A00 throughA63 of the data storage device; when, in contrast, the control signal Cof the multiplexer MUX has the value 1, then the data stored in thememory cells SZ16 through SZ79 are through-connected onto the outputterminals A00 through A63 of the data storage device.

In both instances, 64 data bits are output from the data storage devicein response to a data output request. However, the origin of the datathat are output differs because the output start address in the case ofC=1 is greater by the offset (16 in this case) then the output startaddress in the case C=0.

The displaceability of the output start address as needed provesadvantageous particularly when, due to the appertaining data outputrequest, the command following a branch instruction or the like is to beread, and the data representing this command begin at a location thatlies relatively far behind the data word normally output (withoutshifting the output start address). A command, namely, that could onlybe partially retrieved via a normal data output request can then becompletely retrieved with a single access onto the data storage device.

This, for example, is the case when the memory cells SZ55 through SZ71represent the first command B1 that is to be implemented following abranch or the like.

If one wished to retrieve the command B1 “normally”, i.e. withoutshifting the output start address, two accesses would have to ensue ontothe data storage device because only the first byte of the (2-byte)command B1 could be obtained by the first access. When, in contrast, thecommand B1 is retrieved with an output start address shifted by at leastone byte, then the command B1 can be completely retrieved with a singleaccess onto the data storage device.

The extent to which the output start address is shifted by theadaptation data is determined in the example under consideration by thewiring of the multiplexer MUX and can be arbitrarily determined in termsof operational sign and amount.

The practical realization of an arrangement with which the bits 0through 63 or the bits 32 through 95 of a memory cell field row areoptionally through-connected onto the output terminals of the datastorage device (offset y=32) is shown in FIG. 2.

The structure of the arrangement according to FIG. 2 essentiallycorresponds to the structure of the arrangement according to FIG. 1;differences exist “only” in the wiring of the input terminals of themultiplexer MUX.

In the example under consideration, the shift of the output startaddress by 32 bits proves even more advantageous because the command B1following the branch instruction and, further, the command B2 followingthereupon and stored in memory cells SZ72 through SZ88 in the exampleunder consideration can be completely obtained by a single access ontothe data storage device.

This, however, does not mean that an offset of 32 is generally moreadvantageous than other offsets. Which offset is optimum particularlydepends on the amount of data that is output per data output request andon the lengths of the commands to be carried out.

The data storage device can also be constructed such that the offsetemployed can be varied in terms of operational sign and/or amount, sothat the offset can be individually selected dependent on therespectively current conditions (upon employment of adaptation datacovering a plurality of bits).

When the offset, as in the exemplary embodiment illustrated in FIG. 2,is to be exactly half the size of the plurality of data bits output inresponse to a data output request, the adaptation data (respectivelycovering one bit in the examples illustrated in FIGS. 1 and 2) can bereplaced by an additional (address) bit in the address data applied tothe data storage device.

For the sake of completeness, let it be mentioned that it is compulsoryfor the proper functioning of the arrangements according to FIGS. 1 and2 that more memory cells than there are data bits to be output must beread out when reading data out from the data storage device. Since,however, all memory cells of the selected memory cell field row arealready usually read out given known data storage devices, nomodifications or—at most—no more significant modifications of the datastorage devices are required.

Let it also be pointed out that, when reading data stored at the startand/or at the end of a memory cell field row, it can occur that only apart of the data that are output is valid. Handling this particularcharacteristic, however, does not represent a problem. The fact that thedata that are output are only partly valid can, for example, be signaledby a corresponding identifier (flag).

It should also be obvious that, in instances wherein the datarepresenting a command proceed beyond the end of a memory cell field row(are continued in the next memory cell field row), two accesses onto thedata storage device must still be carried out in order to completelyretrieve the appertaining command.

Nonetheless, the plurality of accesses required in order to readspecific data out can be reduced to a minimum by a data storage deviceconstructed in the way described or similar thereto.

LIST OF REFERENCE CHARACTERS

-   SZFZ Memory cell field row-   SZxx Memory cell xx within a memory cell field row-   B1 First command that is to be carried out after a branch-   B2 Second command that is to be carried out after a branch-   MUX Multiplexer-   C Multiplexer control signal (=adaptation data)-   Ayy Output terminal yy of the data storage device

1. A data storage device in a single integrated circuit unit,comprising: memory cells having stored data with selectable output startaddresses; said data storage device in a single integrated circuit unitcomprising input and output terminals; wherein said storage deviceresponds to a single data output request provided to said input of saidsingle integrated circuit by outputting, via an internal throughconnection of said integrated circuit configured to adaptively connectbits of said memory cells to the output terminals, said stored data fromsaid output terminals of said single integrated circuit beginning with aselected output start address that is one of said selectable outputstart addresses; and wherein said selectable output start addresses ofsaid memory cells are spaced from one another such that an amount ofdata that can be stored between neighboring output start addresses issmaller than an amount of data output in response to said data outputrequest.
 2. A data storage device according to claim 1, wherein saidselected output start address is determined utilizing address dataapplied to said input of said data storage device.
 3. A data storagedevice according to claim 2, wherein: said selected output start addressis determined by further utilizing adaptation data applied to said datastorage device and; said adaptation data is related both to said outputstart address to be employed and an address that is defined by saidaddress data.
 4. A data storage device according to claim 3, furthercomprising: a control mechanism of an interface at which said adaptationdata are used to control said interface.
 5. A data storage deviceaccording to claim 4, wherein said interface comprises a multiplexerthat is driven based on the adaptation data.
 6. A data storage deviceaccording to claim 4, wherein data stored with an output start addressselected from the group consisting of a first output start address and asecond output start address are through-connected.
 7. A data storagedevice according to claim 6, wherein said first output start address isan address that is represented by said address data applied to said datastorage device.
 8. A data storage device, comprising: memory cellshaving stored data with selectable output start addresses; wherein saidstorage device responds to a data output request by outputting saidstored data beginning with a selected output start address; whereinselectable output start addresses are spaced from one another such thatan amount of data that can be stored between neighboring output startaddresses is smaller than an amount of data output in response to saiddata output request; wherein said selected output start address isdetermined utilizing address data applied to said data storage device;wherein said selected output start address is determined by furtherutilizing adaptation data applied to said data storage device; whereinsaid adaptation data is related both to said output start address to beemployed and an address that is defined by said address data; the datastorage device further comprising: output terminals; and an interfaceprovided between memory cells of said data storage device and saidoutput terminals; wherein said adaptation data are used to control saidinterface; wherein data stored with an output start address selectedfrom the group consisting of a first output start address and a secondoutput start address are through-connected; and wherein said secondoutput start address is related to, but different from, said firstoutput start address by a scope defined by a wiring of a multiplexer. 9.A method for outputting data from a data storage device in a singleintegrated circuit unit, comprising the steps of: receiving a singledata output request by said data storage device provided to said inputof said single integrated circuit; and outputting stored data, via aninternal through connection of said integrated circuit configured toadaptively connect bits of the memory cells to said output terminals,from said output terminals of said single integrated circuit, in aquantity of data that is greater than a quantity of data that can bestored between neighboring output start addresses of said memory cells,and beginning said outputting of stored data with a selected outputstart address which is one of said output start addresses.
 10. Themethod according to claim 9, further comprises the steps of: applyingaddress data to said data storage device; and determining said selectedoutput start address by utilizing said address data.
 11. The methodaccording to claim 10, further comprising the step of: defining adaptiondata as an indicia related to said address data and said output startaddress; applying said adaption data to said data storage device,wherein said step of determining said selected output start addressutilizes said adaption data.
 12. The method according to claim 11,further comprising the step of: controlling, with said adaption data,said internal through connection provided between memory cells of saiddata storage device and said output terminals of said data storagedevice.
 13. The method according to claim 12, further comprising thesteps of: controlling a multiplexer contained within said interface byapplying said adaption data; and through-connecting, via saidmultiplexer, data stored within said data storage device beginning withan address selected from the group consisting of a first output startaddress and a second output start address.
 14. The method according toclaim 13, further comprising the step of calculating said first outputstart address from said address data applied to said data storagedevice.
 15. A method for outputting data from a data storage device,comprising the steps of: receiving a data output request by said datastorage device; outputting stored data in a quantity of data that isgreater than a quantity of data that can be stored between neighboringoutput start addresses, and beginning said outputting of stored datawith a selected output start address which is one of said output startaddresses; applying address data to said data storage device;determining said selected output start address by utilizing said addressdata; defining adaption data as an indicia related to said address dataand said output start address; applying said adaption data to said datastorage device, wherein said step of determining said selected outputstart address utilizes said adaption data; controlling, with saidadaption data, an interface provided between memory cells of said datastorage device and output terminals of said data storage device;controlling a multiplexer contained within said interface by applyingsaid adaption data; through-connecting, via said multiplexer, datastored within said data storage device beginning with an addressselected from the group consisting of a first output start address and asecond output start address; and wiring said multiplexer so that saidsecond output start address is related to, but different from, saidfirst output start address by a scope defined by said wiring.
 16. A datastorage device in a single integrated circuit unit, comprising: memorycells having stored data with selectable output start addresses; saiddata storage device in a single integrated circuit unit comprising inputand output terminals; wherein said storage device responds to a singledata output request provided to said input of said single integratedcircuit by outputting, via an internal through connection of saidintegrated circuit, said stored data from said output terminals of saidsingle integrated circuit beginning with a selected output start addressthat is one of said selectable output start addresses; and whereinselectable output start addresses are spaced from one another such thatan amount of data that can be stored between neighboring output startaddresses is smaller than an amount of data output in response to saiddata output request; and wherein the device is selected from the groupconsisting of a RAM, a ROM, EPROM and flash EPROM.